1. Field of the Invention
The present invention generally relates to a test board which is used for testing semiconductor integrated circuit devices, and more particularly to a test board having a plurality of power supply wiring patterns for testing semiconductor integrated circuit devices which have a large number of input/output (I/O) pins.
2. Description of the Related Art
As semiconductor integrated circuit (IC) devices become more highly integrated to achieve multifunction capability, they require an increasing number of input/out (I/O) pins. In particular, ASICs (Application Specific ICs), comprising gate arrays and standard cells that form the user-specified ICs on a semiconductor wafer, require many I/O pins, unlike common IC devices which are developed, manufactured, and sold with the functions and specifications designated by the semiconductor device manufacturer.
According to the pressing demand to meet these requirements, current packaging technology has developed products having 208 I/O pins or more. However, the size of the semiconductor chip or the chip package has not increased in proportion to the increase in the number of I/O pins, because electronic systems using the IC devices have been increasingly miniaturized. These conflicting trends, that is, the need to accommodate greater functionality and a larger number of I/O pins in a smaller package, makes it difficult to design the wiring patterns for sending a test signal to the IC device having a large number of I/O pins, and to design the wiring patterns through which the output signal from the test board is to be measured.
In particular, in a test board having a capacity of up to 50% of the total number of pins of an IC device having 200 I/O pins or more, it is difficult to keep the power supply wiring patterns from contacting other wiring patterns.